**Half Adder-**

- Half Adder is a combinational logic circuit that is used for the purpose of adding two single bit numbers.
- It contains 2 inputs and 2 outputs (sum and carry).

**Designing a Half Adder-**

**Step-01:**

Identify the input and output variables-

- Input variables = A , B (either 0 or 1)
- Output variables = S , C where S = Sum and C = Carry

**Step-02:**

Draw the truth table-

Inputs | Outputs | ||

A | B | C (Carry) | S (Sum) |

0 | 0 | 0 | 0 |

0 | 1 | 0 | 1 |

1 | 0 | 0 | 1 |

1 | 1 | 1 | 0 |

**Truth Table**

**Step-03:**

Draw the K-maps using the above truth table and determine the simplified Boolean expressions-

**Step-04:**

Draw the logic diagram-

**Logic Diagram**

Here, Half Adder has been implemented using 1 XOR gate and 1 AND gate.

**Limitation of Half Adder-**

Half Adders have no scope of adding the carry bit resulting from the addition of previous bits.

This is a major drawback of half adders because real time scenarios involve adding the multiple number of bits which can not be accomplished using half adders.

To overcome this drawback, **Full Adder** comes into play.

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