Carry Look Ahead Adder
 In Ripple Carry Adder, each full adder has to wait for its carryin from its previous stage full adder to start its operation which causes an unnecessary delay.
 Carry Look Ahead Adder is an improved version of the ripple carry adder which generates the carryin of each full adder simultaneously without causing any delay.
Logic Diagram for Carry Look Ahead Adder
Working of Carry Look Ahead Adder
 The working of carry look ahead adder is based on the principle that the carryin of any stage full adder is independent of the carry bits generated during intermediate stages and is only dependent of the following two parameters
 Bits being added in the previous stages
 Carry provided in the beginning
 Since, the above two parameters are always known, the carryin of any stage full adder can be evaluated at any instant of time. Thus, a full adder need not wait until its carryin is generated by its previous stage full adder.
Example
Suppose we want to add two 4bit binary numbers A_{3}A_{2}A_{1}A_{0} and B_{3}B_{2}B_{1}B_{0}
They will be added as
From here, we have
C_{1} = C_{0} (A_{0} ⊕ B_{0}) + A_{0}B_{0}
C_{2} = C_{1} (A_{1} ⊕ B_{1}) + A_{1}B_{1}
C_{3} = C_{2} (A_{2} ⊕ B_{2}) + A_{2}B_{2}
C_{4} = C_{3} (A_{3} ⊕ B_{3}) + A_{3}B_{3}
For simplicity, Let
 G_{i} = A_{i}B_{i} where G is called carry generator
 P_{i} = A_{i} ⊕ B_{i} where P is called carry propagator
Then, rewriting the equations, we have
C_{1} = C_{0}P_{0} + G_{0 }………….. (1)
C_{2} = C_{1}P_{1} + G_{1}_{ }………….. (2)
C_{3} = C_{2}P_{2} + G_{2}_{ }………….. (3)
C_{4} = C_{3}P_{3} + G_{3}_{ }………….. (4)
Now, let us remove C_{1}, C_{2} and C_{3} from RHS of every equation as these are intermediate carry bits.
Substituting (1) in (2), we will get C_{2} in terms of C_{0} and then substituting (2) in (3), we will get C_{3} in terms of C_{0} and so on.
Finally, we will have the following equations showing that the carry in of any stage depends only on the bits being added in previous stages and the carry bit which was provided in the beginning
 C_{1} = C_{0}P_{0} + G_{0 }
 C_{2} = C_{0}P_{0}P_{1} + G_{0}P_{1} + G_{1}
 C_{3} = C_{0}P_{0}P_{1}P_{2} + G_{0}P_{1}P_{2} + G_{1}P_{2} + G_{2}
 C_{4} =C_{0}P_{0}P_{1}P_{2}P3 + G_{0}P_{1}P_{2}P_{3} + G_{1}P_{2}P_{3} + G_{2}P_{3} + G_{3}
Trick to memorize the above equations
Consider any above equation. Let us consider the equation for generating carry bit C_{2}.
Now, if we consider the carry bit C_{2}, then there are three possible reasons for its generation as shown in the following picture
In the similar manner, we can write other equations as well very easily.
Implementation of the carry generator circuits
The above carry generator circuits are usually implemented as two level combinational circuits using AND and OR gates where gates are assumed to have any number of inputs.
Implementation of C_{1}–
C_{1} = C_{0}P_{0} + G_{0 }
Implementation of C_{1} requires 1 AND gate and 1 OR gate.
Implementation of C_{2}–
C_{2} = C_{0}P_{0}P_{1} + G_{0}P_{1} + G_{1}
Implementation of C_{2} requires 2 AND gates and 1 OR gate.
Implementation of C_{3} and C_{4}–
Similarly, we can implement C_{3} and C_{4}.
 Implementation of C_{3} will require 3 AND gates and 1 OR gate.
 Implementation of C_{4 }will require 4 AND gates and 1 OR gate.
Thus, total number of gates required for implementing carry generators (provided carry propagators P_{i} and carry generators G_{i}) are
Total number of AND gates required for addition of 4bit numbers = 1 + 2 + 3 + 4 = 10
Total number of OR gates required for addition of 4bit numbers = 1 + 1 + 1 + 1 = 4
General formula
For a nbit carry look ahead adder to evaluate all the carry bits, we require

Need of Carry Look Ahead Adder
 In ripple carry adder, we have a cascade of n full adders and each full adder has to wait for its carryin from its previous stage full adder to continue its operation.
 Thus, n^{th} full adder has to wait until all (n1) full adders have completed their operations which causes a delay and makes ripple carry adder extremely slow.
 The situation becomes worst when the value of n becomes very large.
 To overcome this delay, we use carry look ahead adder in which carry for each full adder is generated simultaneously without any delay.
Advantage of Carry Look Ahead Adder
 The advantage of carry look ahead adder is that it reduces propagation delay.
Disadvantage of Carry Look Ahead Adder
 The disadvantage of carry look ahead adder is that it involves complex hardware.
 Because it involves complex hardware, it is costlier and it gets complicated as the number of bits increases.
Time Complexity
Time complexity of Carry Look Ahead Adder = Θ (logn)
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