Ripple Carry Adder
Before you go through this article, make sure that you have gone through the previous article on Ripple Carry Adder.
In Ripple Carry Adder,
 Each full adder has to wait for its carryin from its previous stage full adder.
 Thus, n^{th} full adder has to wait until all (n1) full adders have completed their operations.
 This causes a delay and makes ripple carry adder extremely slow.
 The situation becomes worst when the value of n becomes very large.
 To overcome this disadvantage, Carry Look Ahead Adder comes into play.
In this article, we will discuss about Carry Look Ahead Adder.
Carry Look Ahead Adder
 Carry Look Ahead Adder is an improved version of the ripple carry adder.
 It generates the carryin of each full adder simultaneously without causing any delay.
 The time complexity of carry look ahead adder = Θ (logn).
Logic Diagram
The logic diagram for carry look ahead adder is as shown below
Carry Look Ahead Adder Working
The working of carry look ahead adder is based on the principle The carryin of any stage full adder is independent of the carry bits generated during intermediate stages. 
The carryin of any stage full adder depends only on the following two parameters
 Bits being added in the previous stages
 Carryin provided in the beginning
Now,
 The above two parameters are always known from the beginning.
 So, the carryin of any stage full adder can be evaluated at any instant of time.
 Thus, any full adder need not wait until its carryin is generated by its previous stage full adder.
Also ReadFull Adder Working
4Bit Carry Look Ahead Adder
Consider two 4bit binary numbers A_{3}A_{2}A_{1}A_{0} and B_{3}B_{2}B_{1}B_{0} are to be added.
Mathematically, the two numbers will be added as
From here, we have
C_{1} = C_{0} (A_{0} ⊕ B_{0}) + A_{0}B_{0}
C_{2} = C_{1} (A_{1} ⊕ B_{1}) + A_{1}B_{1}
C_{3} = C_{2} (A_{2} ⊕ B_{2}) + A_{2}B_{2}
C_{4} = C_{3} (A_{3} ⊕ B_{3}) + A_{3}B_{3}
For simplicity, Let
 G_{i} = A_{i}B_{i} where G is called carry generator
 P_{i} = A_{i} ⊕ B_{i} where P is called carry propagator
Then, rewriting the above equations, we have
C_{1} = C_{0}P_{0} + G_{0 }………….. (1)
C_{2} = C_{1}P_{1} + G_{1}_{}………….. (2)
C_{3} = C_{2}P_{2} + G_{2}_{}………….. (3)
C_{4} = C_{3}P_{3} + G_{3}_{}………….. (4)
Now,
 Clearly, C1, C2 and C3 are intermediate carry bits.
 So, let’s remove C_{1}, C_{2} and C_{3} from RHS of every equation.
 Substituting (1) in (2), we get C_{2} in terms of C_{0}.
 Then, substituting (2) in (3), we get C_{3} in terms of C_{0} and so on.
Finally, we have the following equations
 C_{1} = C_{0}P_{0} + G_{0 }
 C_{2} = C_{0}P_{0}P_{1} + G_{0}P_{1} + G_{1}
 C_{3} = C_{0}P_{0}P_{1}P_{2} + G_{0}P_{1}P_{2} + G_{1}P_{2} + G_{2}
 C_{4} =C_{0}P_{0}P_{1}P_{2}P3 + G_{0}P_{1}P_{2}P_{3} + G_{1}P_{2}P_{3} + G_{2}P_{3} + G_{3}
These equations are important to remember.
These equations show that the carryin of any stage full adder depends only on
 Bits being added in the previous stages
 Carry bit which was provided in the beginning
Trick To Memorize Above Equations
As an example, let us consider the equation for generating carry bit C_{2}.
There are three possible reasons for generation of C_{2} as depicted in the following picture
In the similar manner, we can write other equations as well very easily.
Implementation Of Carry Generator Circuits
The above carry generator circuits are usually implemented as
 Two level combinational circuits.
 Using AND and OR gates where gates are assumed to have any number of inputs.
Implementation Of C_{1}–
 The carry generator circuit for C1 is implemented as shown below.
 It requires 1 AND gate and 1 OR gate.
C_{1} = C_{0}P_{0} + G_{0}
Implementation Of C_{2}–
 The carry generator circuit for C2 is implemented as shown below.
 It requires 2 AND gates and 1 OR gate.
C_{2} = C_{0}P_{0}P_{1} + G_{0}P_{1} + G_{1}
Implementation Of C_{3} & C_{4}–
Similarly, we implement C_{3} and C_{4}.
 Implementation of C_{3} uses 3 AND gates and 1 OR gate.
 Implementation of C_{4 }uses 4 AND gates and 1 OR gate.
Total number of gates required to implement carry generators (provided carry propagators P_{i} and carry generators G_{i}) are
 Total number of AND gates required for addition of 4bit numbers = 1 + 2 + 3 + 4 = 10.
 Total number of OR gates required for addition of 4bit numbers = 1 + 1 + 1 + 1 = 4.
General Formula
The following formula is used to calculate number of gates required for evaluating all carry bits
For a nbit carry look ahead adder to evaluate all the carry bits, it requires

Advantages of Carry Look Ahead Adder
The advantages of carry look ahead adder are
 It generates the carryin for each full adder simultaneously.
 It reduces the propagation delay.
Disadvantages of Carry Look Ahead Adder
The disadvantages of carry look ahead adder are
 It involves complex hardware.
 It is costlier since it involves complex hardware.
 It gets more complicated as the number of bits increases.
To gain better understanding about Carry Look Ahead Adder,
Next ArticleK Maps  Karnaugh Maps
Get more notes and other study material of Digital Design.
Watch video lectures by visiting our YouTube channel LearnVidFun.