Delay in Ripple Carry Adder
Before you go through this article, make sure that you have gone through the previous article which discusses about Ripple Carry Adder and its working.
Suppose we have a Nbit ripple carry adder as shown
Type01 Problem:
You will be given the carry propagation delay and sum propagation delay of each full adder and you will be asked to calculate the worst case delay of the ripple carry adder.
Solution
Know these terms?

 We know, In ripple carry adder, a full adder becomes active only when its carry in is made available by its adjacent less significant full adder.
 When carry in becomes available to the full adder, it starts its operation and produces the corresponding output sum bit and carry bit.
If you are asked to calculate the time after which the output sum bit or carry bit becomes available from any particular full adder, then you can calculate it as
Time after which carry bit C_{x} becomes available
Required time
= Total number of full adders till full adder producing C_{x} X Carry propagation delay of a full adder
Time after which sum bit S_{x} becomes available
Required time
= Time taken for its carry in to become available + Sum propagation delay of a full adder
= { Total number of full adders before full adder producing S_{x} X Carry propagation delay of a full adder } + Sum propagation delay of a full adder
NOTE
We will calculate the worst case delay for the last full adder.
Type02 Problem:
You will be given the propagation delay of basic logic gates and you will be told how the full adder has been implemented and then you will be asked to calculate the worst case delay of ripple carry adder.
Suppose each full adder in ripple carry adder is implemented as
Solution
We have to compute everything in the same manner as we did in the type01 problem. It’s just that in Type02 problem, one step is increased.
We will first calculate the carry propagation delay and sum propagation delay in terms of propagation delays of basic logic gates and then our problem will be reduced to Type01 problem.
Let
 Propagation delay of AND gate = T_{pd }(AND)
 Propagation delay of OR gate = T_{pd }(OR)
 Propagation delay of XOR gate = T_{pd }(XOR)
Calculating carry propagation delay
We will calculate the carry propagation delay of a full adder using its carry generator logic circuit which in the given implementation has 2 levels.
 At the first level, three AND gates operate. Because all the three AND gates operate in parallel, so we will consider the propagation delay due to only one AND gate and not because of all the three AND gates.
 At the second level, OR gate operates.
Now,
Carry propagation delay of a full adder which is the time taken by it to generate the output carry bit is given by
Carry propagation delay
= Propagation delay of AND gate + Propagation delay of OR gate
= T_{pd }(AND) + T_{pd }(OR)
Calculating sum propagation delay
We will calculate the sum propagation delay of a full adder using its sum generator logic circuit which in the given implementation has only 1 level at which the XOR gate operates.
Now,
Sum propagation delay of a full adder which is the time taken by it to generate the output sum bit is given by
Sum propagation delay
= Propagation delay of XOR gate
= T_{pd }(XOR)
Now, after we have got the carry propagation delay and sum propagation delay of full adders, our problem reduces to Type01 problem.
Now, we will use the same formulas we have learnt in Type01 problem to make the required calculations.
NOTE
If in the question, it was said that while implementing the sum generator logic circuit of full adders, only 2input XOR gates are used, then in that case we would require two such XOR gates which would work at 2 levels. So, in that case, sum propagation delay would be twice the propagation delay of XOR gate.
PRACTICE PROBLEMS BASED ON CALCULATING DELAY IN RIPPLE CARRY ADDER
Problem01:
A 16bit ripple carry adder is realized using 16 identical full adders. The carry propagation delay of each full adder is 12 ns and the sum propagation delay of each full adder is 15 ns. The worst case delay of this 16 bit adder will be ______?
A) 195 ns
B) 220 ns
C) 250 ns
D) 300 ns
Solution
We will consider the last full adder for worst case delay.
Time after which output carry bit becomes available from the last full adder
= Total number of full adders X Carry propagation delay of a full adder
= 16 x 12 ns
= 192 ns
Time after which output sum bit becomes available from the last full adder
= Time taken for its carry in to become available + Sum propagation delay of a full adder
= { Total number of full adders before last full adder X Carry propagation delay of a full adder } + Sum propagation delay of a full adder
= { 15 x 12 ns } + 15 ns
= 195 ns
Thus, Option (A) is correct.
For more explanation, Watch this video solution.
Problem02:
Following figure shows the implementation of full adders in a 16bit ripple carry adder realized using 16 identical full adders. The propagation delay of the XOR, AND and OR gates are 20 ns, 15 ns and 10 ns respectively. The worst case delay of this 16 bit adder will be ______?
A) 395 ns
B) 220 ns
C) 400 ns
D) 300 ns
Solution
We will consider the last full adder for worst case delay.
Time after which output carry bit becomes available from the last full adder
= Total number of full adders X Carry propagation delay of a full adder
= Total number of full adders X { Propagation delay of AND gate + Propagation delay of OR gate }
= 16 x { 15 ns + 10 ns }
= 16 x 25 ns
= 400 ns
Time after which output sum bit becomes available from the last full adder
= Time taken for its carry in to become available + Sum propagation delay of a full adder
= { Total number of full adders before last full adder X Carry propagation delay of a full adder } + Propagation delay of XOR gate
= { 15 x (15 ns + 10 ns) } + 20 ns
= 395 ns
Thus, Option (C) is correct.
Also practice: An advance level problem based on calculating delay in ripple carry adder
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